US 12,260,838 B2
Display apparatus and electronic device
Kazunori Watanabe, Machida (JP); and Koji Kusunoki, Isehara (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Aug. 18, 2023, as Appl. No. 18/235,498.
Application 18/235,498 is a continuation of application No. 17/425,766, granted, now 11,735,134, previously published as PCT/IB2020/050458, filed on Jan. 22, 2020.
Claims priority of application No. 2019-018781 (JP), filed on Feb. 5, 2019.
Prior Publication US 2023/0395036 A1, Dec. 7, 2023
Int. Cl. G09G 3/30 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); G09G 3/36 (2006.01); G11C 19/28 (2006.01)
CPC G09G 3/3677 (2013.01) [G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); G09G 3/3611 (2013.01); G11C 19/28 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A display apparatus comprising:
a shift register;
a boosting circuit; and
a pixel,
wherein the shift register comprises a first output terminal, a second output terminal, and a third output terminal,
wherein the boosting circuit comprises a first transistor, a second transistor, and a first capacitor,
wherein the pixel comprises a third transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one electrode of the first capacitor,
wherein the one electrode of the first capacitor is electrically connected to one of a source and a drain of the second transistor,
wherein the one electrode of the first capacitor is electrically connected to a gate of the third transistor,
wherein the one of the source and the drain of the first transistor, the one electrode of the first capacitor, and the one of the source and the drain of the second transistor are electrically connected to one another,
wherein a gate of the first transistor is electrically connected to the first output terminal,
wherein the other electrode of the first capacitor is electrically connected to the second output terminal, and
wherein a gate of the second transistor is electrically connected to the third output terminal.