US 12,260,828 B2
Gate driving circuit and display device
Jaesung Park, Paju-si (KR); and Kwangsoo Kim, Incheon (KR)
Assigned to LG Display Co., Ltd., Seoul (KR)
Filed by LG Display Co., Ltd., Seoul (KR)
Filed on Nov. 14, 2023, as Appl. No. 18/508,340.
Claims priority of application No. 10-2022-0168037 (KR), filed on Dec. 5, 2022.
Prior Publication US 2024/0185799 A1, Jun. 6, 2024
Int. Cl. G09G 3/3266 (2016.01)
CPC G09G 3/3266 (2013.01) [G09G 2300/0408 (2013.01); G09G 2310/0291 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A gate driving circuit comprising a plurality of stage circuits electrically connected to a plurality of clock signal lines and configured to output a plurality of scan signals and a plurality of carry signals,
wherein the plurality of clock signal lines include first, second, third, fourth, fifth, sixth, seventh, and eighth scan clock signal lines and first and second carry clock signal lines,
each of the plurality of stage circuits includes:
a buffer group configured to output one or more scan signals of the plurality of scan signals and one or more carry signals of the plurality of carry signals;
a logic part configured to control the buffer group during a display driving period for driving an image; and
a sensing part configured to control the buffer group during a sensing driving period for sensing a characteristic value of a sub-pixel, and
the plurality of stage circuits include:
a first stage circuit electrically connected to the first, second, third and fourth scan clock signal lines and the first carry clock signal line;
a second stage circuit electrically connected to the fifth, sixth, seventh, and eighth scan clock signal lines and the second carry clock signal line; and
a third stage circuit electrically connected to the first, second, third, and fourth scan clock signal lines and the first carry clock signal line.