US 12,260,827 B2
Display device including scan driver controlled by clock signals
Jinyoung Roh, Yongin-si (KR); Bon-Seog Gu, Yongin-si (KR); Hae-Kwan Seo, Yongin-si (KR); and Jaekeun Lim, Yongin-si (KR)
Assigned to SAMSUNG DISPLAY CO., LTD., Yongin-si (KR)
Filed by SAMSUNG DISPLAY CO., LTD., Yongin-si (KR)
Filed on May 25, 2023, as Appl. No. 18/323,887.
Claims priority of application No. 10-2022-0104628 (KR), filed on Aug. 22, 2022.
Prior Publication US 2024/0062723 A1, Feb. 22, 2024
Int. Cl. G09G 3/3266 (2016.01); G09G 3/20 (2006.01); G09G 3/32 (2016.01)
CPC G09G 3/3266 (2013.01) [G09G 3/2003 (2013.01); G09G 3/32 (2013.01); G09G 2300/0452 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/08 (2013.01); G09G 2330/021 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A display device comprising:
a display panel including a plurality of pixels, a plurality scan lines, and a plurality of data lines;
a scan driver configured to provide scan signals to the plurality of scan lines; and
a data driver configured to provide data signals to the plurality of data lines,
wherein the scan driver comprises:
a first sub-scan driver configured to receive a first start signal, a first odd clock signal and a second odd clock signal, where a phase difference between the first and second odd clock signals is a horizontal period; and
a second sub-scan driver configured to receive a second start signal, a first even clock signal and a second even clock signal, where a phase difference between the first and second even clock signals is the horizontal period,
wherein each of the scan signals has an activation period corresponding to a horizontal period,
wherein each of the first and second odd clock signals includes a first clock enable period, which is ‘k’ times the horizontal period, and a first clock disable period, which is ‘k’ times the horizontal period, wherein each of the first and second odd clock signals toggles between a first logic state and a second other logic state each time the horizontal period elapses during the first clock enable period, and maintains the first logic state during the first clock disable period,
wherein each of the first and second even clock signals includes a second clock enable period, which is ‘k’ times the horizontal period, and a second clock disable period, which is ‘k’ times the horizontal period, wherein each of the first and second even clock signals toggles between the first logic state and the second logic state each time the horizontal period elapses during the second clock enable period, and maintains the first logic state during the second clock disable period,
wherein the first clock enable period alternates with the second clock enable period, and the ‘k’ is an integer greater than or equal to 2,
wherein color information of the data signal provided to at least one data line among the data lines is changed in units of time corresponding to ‘k’ times the horizontal period,
wherein the first start signal includes an activation period that does not overlap the first clock enable period, and
wherein the second start signal includes an activation period that does not overlap the second clock enable period,
wherein the first and second odd clock signals have different numbers of activation periods within the first clock enable period, and
wherein the first and second even clock signal have different numbers of activation periods within the second clock enable period.