| CPC G09G 3/3258 (2013.01) [G09G 3/32 (2013.01); G09G 3/3266 (2013.01); G09G 3/3291 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0275 (2013.01); G09G 2310/08 (2013.01)] | 19 Claims |
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1. A pixel driving circuit, comprising a driving transistor and a data writing module, wherein,
a first control terminal of the data writing module is connected to a first control signal, a second control terminal of the data writing module is connected to a second control signal, an input terminal of the data writing module is connected to a data voltage, and the data writing module is further electrically connected to a gate, a first electrode and a second electrode of the driving transistor;
a driving timing of the pixel driving circuit includes a writing frame including a first data writing phase and a second data writing phase in sequence, and the data voltage includes an active data voltage and a first data compensation voltage; and
the data writing module is configured to write the first data compensation voltage into the gate, the first electrode, and the second electrode of the driving transistor in the first data writing phase, and to write the active data voltage into the gate, the first electrode, and the second electrode of the driving transistor in the second data writing phase;
wherein the driving timing of the pixel driving circuit further includes a third data writing phase after the second data writing phase;
wherein, in the writing frame, the first control signal includes three first pulses and the second control signal includes two second pulses; and
in the driving timing of the pixel driving circuit, first one of the first pulses and first one of the second pulses are located in the first data writing phase and at least partially overlapped with each other, second one of the first pulses and second one of the second pulses are located in the second data writing phase and at least partially overlapped with each other, and third one of the first pulses is located in the third data writing phase.
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