US 12,260,820 B2
Pixel circuit and display device including the same
Ki Min Son, Paju-si (KR); and Chang Hee Kim, Paju-si (KR)
Assigned to LG Display Co., Ltd., Seoul (KR)
Filed by LG DISPLAY CO., LTD., Seoul (KR)
Filed on Sep. 18, 2023, as Appl. No. 18/369,257.
Application 18/369,257 is a division of application No. 17/852,906, filed on Jun. 29, 2022, granted, now 11,798,476.
Claims priority of application No. 10-2021-0089997 (KR), filed on Jul. 8, 2021; and application No. 10-2021-0166801 (KR), filed on Nov. 29, 2021.
Prior Publication US 2024/0013720 A1, Jan. 11, 2024
Int. Cl. G09G 3/3233 (2016.01); G09G 3/3266 (2016.01); G09G 3/3283 (2016.01)
CPC G09G 3/3233 (2013.01) [G09G 3/3266 (2013.01); G09G 3/3283 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/0297 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A display device comprising:
a display panel on which a plurality of data lines, a plurality of gate lines intersecting the plurality of data lines, a plurality of power lines, and a plurality of pixel circuits connected to the data lines, the gate lines, and the power lines are disposed;
a data driver configured to supply a data voltage of pixel data to the data lines; and
a gate driver configured to supply a gate signal to the gate lines,
wherein each of the pixel circuits comprises:
a driving transistor comprising a first electrode connected to a first node to which a pixel driving voltage is applied, a first gate electrode connected to a second node, a second electrode connected to a third node, and a second gate electrode connected to a fourth node, and configured to supply an electric current to a light-emitting diode;
a first switch transistor configured to be turned on according to a gate-on voltage of the gate signal and supply the data voltage to the second node connected to the first gate electrode;
a first capacitor connected between the second node and the third node;
a second capacitor including a first electrode directly connected to the third node and a second electrode directly connected to the fourth node to which a reference voltage is applied; and
a third capacitor connected between the fourth node and the first node or between the fourth node and a first power line to which the pixel driving voltage is applied.