| CPC G09G 3/3233 (2013.01) [G09G 3/3266 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/061 (2013.01); G09G 2310/08 (2013.01)] | 19 Claims |
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1. A display panel comprising a display area and a non-display area, wherein the display area comprises pixel units arranged in array, at least one of the pixel units comprises a sub-pixel of a first color, a sub-pixel of a second color and a sub-pixel of a third color, the first color, the second color and the third color are different colors, at least one sub-pixel comprises a pixel circuit and a light emitting element, and the pixel circuit is connected to an anode of the light emitting element; the non-display area comprises an anode voltage driving circuit connected to a sub-pixel and configured to provide an anode voltage control signal to a pixel circuit of the connected sub-pixel to provide a voltage signal to the anode of the light emitting element;
the anode voltage driving circuit comprises K anode voltage driving sub-circuits arranged along a row direction; and
each of the anode voltage driving sub-circuits is connected to sub-pixels of at least one color, and different anode voltage driving sub-circuits are connected to sub-pixels of different colors, K being a positive integer greater than or equal to 2;
wherein the display area further comprises 3N column of data signal lines, M rows of scan signal lines, M rows of reset signal lines and M rows of initial voltage lines, wherein M is the total number of rows of pixel units and N is the total number of columns of pixel units;
the pixel circuit comprises a first transistor to a seventh transistor and a storage capacitor;
a control electrode of the first transistor is connected to a reset signal terminal, a first electrode of the first transistor is connected to an initial voltage terminal, a second electrode of the first transistor is connected to a second node, a control electrode of the second transistor is connected to a scan signal terminal, a first electrode of the second transistor is connected to the second node, and a second electrode of the second transistor is connected to a third node; a control electrode of the third transistor is connected to the second node, a first electrode of the third transistor is connected to a first node, and a second electrode of the third transistor is connected to the third node; a control electrode of the fourth transistor is connected to the scan signal terminal, a first electrode of the fourth transistor is connected to a data signal terminal, and a second electrode of the fourth transistor is connected to the first node; a control electrode of the fifth transistor is connected to a light emitting signal terminal, a first electrode of the fifth transistor is connected to a first power terminal, and a second electrode of the fifth transistor is connected to the first node; a control electrode of the sixth transistor is connected to the light emitting signal terminal, a first electrode of the sixth transistor is connected to the third node, and a second electrode of the sixth transistor is connected to the light emitting element; a control electrode of the seventh transistor is connected to an anode voltage control terminal, a first electrode of the seventh transistor is connected to an anode voltage signal terminal, a second electrode of the seventh transistor is connected to the anode of the light emitting element, a first end of the storage capacitor is connected to the first power terminal, and a second end of the storage capacitor is connected to the second node; and
for a pixel circuit of a sub-pixel in row i and column j, the data signal terminal is connected to a data signal line in column j, the scan signal terminal is connected to a scan signal line in row i, the reset signal terminal is connected to a reset signal line in row i, and the initial voltage terminal is connected to an initial voltage line in row i, 1≤i≤M, 1≤j≤3N.
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