| CPC G09G 3/006 (2013.01) [G06F 3/1446 (2013.01); G09G 3/32 (2013.01); G09G 2300/026 (2013.01); G09G 2300/0426 (2013.01); G09G 2330/04 (2013.01); G09G 2330/12 (2013.01)] | 12 Claims |
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1. A display panel comprising:
a substrate;
a plurality of pixel circuits provided on the substrate and, each of the plurality of pixel circuits being configured to drive a respective inorganic light emitting device among a plurality of inorganic light emitting devices;
a test line formed on a first layer of the substrate and extending from an edge of the substrate;
a signal line formed on a second layer of the substrate and connected to the plurality of pixel circuits, the second layer being different from the first layer;
an insulating layer provided on the test line; and
a resistance structure provided on the test line, the resistance structure comprising:
at least two vertical interconnect accesses (vias) passing through the insulating layer; and
a resistance layer provided on the insulating layer and extending between the at least two vias,
wherein the at least two vias connect the test line and the resistance layer to each other, and the test line is discontinuous at an area between the at least two vias,
wherein the resistance layer is configured to receive, through one of the at least two vias, a current applied to the test line,
wherein the insulating layer is formed on a test line layer in which the test line is formed, and the resistance layer is formed on the insulating layer,
wherein the test line has an exposed end at the edge of the substrate,
wherein the plurality of pixel circuits comprises a first pixel circuit configured to drive a first inorganic light emitting device among the plurality of inorganic light emitting devices, and a second pixel circuit configured to drive a second inorganic light emitting device among the plurality of inorganic light emitting devices,
wherein the first pixel circuit is adjacent to the second pixel circuit in a first direction,
wherein the signal line is extended from the first pixel circuit to the second pixel circuit in the first direction,
wherein the test line is extended between the first pixel circuit and the second pixel circuit in a second direction perpendicular to the first direction such that the test line intersects with the signal line, and
wherein the resistance structure is provided between the exposed end of the test line and a point at which the test line and the signal line cross each other.
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