| CPC G06T 7/001 (2013.01) [G06T 7/11 (2017.01); G06T 2207/20081 (2013.01); G06T 2207/30148 (2013.01)] | 20 Claims |

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1. A computerized system of runtime examination of a semiconductor specimen, the system comprising a processing and memory circuitry (PMC) configured to:
obtain a runtime image representative of an inspection area of the semiconductor specimen, the runtime image having a low signal-to-noise ratio (SNR); and
process the runtime image using a machine learning (ML) model to obtain examination data specific for a given examination application, wherein the ML model is previously trained for the given examination application using one or more training samples, each training sample representative of a respective reference area sharing same design pattern as the inspection area and comprising:
a first training image of the respective reference area having a low SNR similar to the low SNR of the runtime image; and
label data indicative of ground truth in the respective reference area pertaining to the given examination application, the label data obtained by annotating a second training image of the respective reference area having a high SNR, wherein the high SNR is defined to ensure a level of annotation accuracy on the second training image while maintaining correspondence between the second training image and the first training image.
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