US 12,260,470 B2
Apparatus and method for managing data bias in a graphics processing architecture
Joydeep Ray, Folsom, CA (US); Abhishek R. Appu, El Dorado Hills, CA (US); Altug Koker, El Dorado Hills, CA (US); and Balaji Vembu, Folsom, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 12, 2023, as Appl. No. 18/536,581.
Application 18/536,581 is a continuation of application No. 17/695,591, filed on Mar. 15, 2022, granted, now 11,847,719.
Application 17/695,591 is a continuation of application No. 16/867,278, filed on May 5, 2020, granted, now 11,282,161, issued on Mar. 22, 2022.
Application 16/867,278 is a continuation of application No. 16/365,056, filed on Mar. 26, 2019, granted, now 10,650,483, issued on May 12, 2020.
Application 16/365,056 is a continuation of application No. 15/482,685, filed on Apr. 7, 2017, granted, now 10,282,811, issued on May 7, 2019.
Prior Publication US 2024/0177264 A1, May 30, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 15/16 (2006.01); G06F 12/0811 (2016.01); G06F 12/0815 (2016.01); G06F 12/0831 (2016.01); G06F 12/0875 (2016.01); G06F 12/0888 (2016.01); G06T 1/20 (2006.01); G06T 1/60 (2006.01)
CPC G06T 1/20 (2013.01) [G06F 12/0811 (2013.01); G06F 12/0815 (2013.01); G06F 12/0831 (2013.01); G06F 12/0875 (2013.01); G06F 12/0888 (2013.01); G06T 1/60 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/302 (2013.01); G06F 2212/455 (2013.01); G06F 2212/621 (2013.01)] 10 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a plurality of graphics processor cores;
a plurality of load/store units;
a memory controller to couple the plurality of graphics processor cores and the plurality of load/store units with a local memory device;
an interconnect to couple a processing device external to the apparatus with the local memory device, the interconnect to ensure that data accessed from the local memory device remains coherent; and
memory management circuitry to map shared virtual memory (SVM) addresses to physical addresses of memory pages in the local memory device and a system memory device,
the memory management circuitry to bias a plurality of the memory pages in favor of access by the plurality of graphics processor cores, wherein the processing device is to maintain accessibility to the biased plurality of memory pages that are in favor of access by the plurality of graphics processor cores.