US 12,260,324 B2
Monolithic multi-bit weight cell for neuromorphic computing
Borna J. Obradovic, Leander, TX (US); Titash Rakshit, Austin, TX (US); Jorge A. Kittl, Austin, TX (US); and Ryan Hatcher, Austin, TX (US)
Assigned to Samsung Electronics Co., Ltd., Yongin-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Dec. 23, 2020, as Appl. No. 17/133,427.
Application 17/133,427 is a continuation of application No. 15/678,050, filed on Aug. 15, 2017, granted, now 10,909,449.
Claims priority of provisional application 62/485,867, filed on Apr. 14, 2017.
Prior Publication US 2021/0117769 A1, Apr. 22, 2021
Int. Cl. G06N 3/04 (2023.01); G06N 3/0442 (2023.01); G06N 3/063 (2023.01); G06N 3/065 (2023.01); G11C 11/54 (2006.01); G11C 11/56 (2006.01); H10B 20/00 (2023.01); H10B 41/27 (2023.01); G06N 3/045 (2023.01); G11C 13/00 (2006.01); H01L 21/762 (2006.01)
CPC G06N 3/065 (2023.01) [G06N 3/04 (2013.01); G06N 3/0442 (2023.01); G06N 3/063 (2013.01); G11C 11/54 (2013.01); G11C 11/56 (2013.01); H10B 20/40 (2023.02); H10B 41/27 (2023.02); G06N 3/045 (2023.01); G11C 13/0069 (2013.01); H01L 21/7624 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A neuromorphic weight cell (NWC) comprising:
resistors connected in series;
shunting nonvolatile memory (NVM) elements coupled in parallel to the resistors; and
input terminals configured to be concurrently and individually controlled by respectively receiving variable voltages, and located respectively between adjacent resistors of a pair of resistors.