US 12,260,320 B2
Dynamic design method to improve the adaptability of acceleration units to neural networks
Shun-Feng Su, Taipei (TW); and Meng-Wei Chang, Taipei (TW)
Assigned to NATIONAL TAIWAN UNIVERSITY OF SCIENCE & TECHNOLOGY, Taipei (TW)
Filed by NATIONAL TAIWAN UNIVERSITY OF SCIENCE AND TECHNOLOGY, Taipei (TW)
Filed on Jun. 30, 2021, as Appl. No. 17/363,141.
Claims priority of application No. 110107860 (TW), filed on Mar. 5, 2021.
Prior Publication US 2022/0284272 A1, Sep. 8, 2022
Int. Cl. G06N 3/063 (2023.01); G06F 7/523 (2006.01); G06F 7/535 (2006.01); G06F 9/50 (2006.01); G06F 17/16 (2006.01); G06F 30/327 (2020.01); G06F 30/34 (2020.01)
CPC G06N 3/063 (2013.01) [G06F 7/523 (2013.01); G06F 7/535 (2013.01); G06F 9/5027 (2013.01); G06F 17/16 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A dynamic design method to improve adaptability of acceleration units to neural networks, wherein the method is implemented on an electronic device installed with an operating system and performed without power-off action, wherein the operating system is for executing application programs during a runtime stage, the method comprising steps of:
generating a plurality of different circuit description files through a neural network model, wherein each of the different circuit description files defines a data format corresponding to an hardware acceleration unit for the neural network model and a circuit logic related to a data segmentation algorithm, wherein the hardware acceleration unit comprises a software-defined hardware chip;
employing a software framework to interpret a model data format of weight values of the neural network model through a process of reading the weight values of the neural network model during the runtime stage of the operating system;
comparing the model data format with the data format defined in each of the different circuit description files to select one circuit description file from the different circuit description files by the software framework during the runtime stage; and
reconfiguring a circuit of the software-defined hardware chip during the runtime stage according to the one circuit description file, so as to dynamically form a reconfigured chip as a reconfigured-hardware acceleration unit adapted to the model data format for the neural network model, wherein the reconfigured chip comprises the circuit logic suitable for running the data segmentation algorithm.