| CPC G06N 3/063 (2013.01) [G06N 3/04 (2013.01); G06N 3/045 (2023.01)] | 13 Claims |
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1. An integrated circuit that comprises:
a neural network processor comprising building blocks, each building block comprising an input and an output and executed by the neural network processor to:
receive, by an input of the building block, input information having a first number (F1) of features;
perform, by one or more first array convolution units of the building block, an expanding group convolution on the input information, to provide a first intermediate information, the first intermediate information having a second number (F2) of features, such that the second number of features exceeds the first number of features, and wherein the expanding group convolution applicable on a first plurality (G1) of groups of the input information;
perform, by one or more second array convolution units of the building block, a group convolution on the first intermediate information, to provide a second intermediate information, the group convolution applicable on a second plurality (G2) of groups of the first intermediate information, G2 exceeds G1;
perform, by one or more third array convolution units of the building block, a condensing group convolution on the second intermediate information, to provide third intermediate information, the group convolution applicable on a first plurality of groups of the input information; and
perform, by one or more fourth array convolution units applied on the third intermediate information, a non-grouped convolution to provide output information; wherein a convolution unit of each of the first array convolution units, the second array convolution units, the third array convolution units and the fourth array convolution units are hardware convolution neural network units,
wherein a ratio between the second plurality of groups of the first intermediate information and the first plurality of groups of the input information differ from a ratio between the second number of features of the first intermediate information and the first number of features of the input information,
wherein each convolution units of the first array convolution units, the second array convolution units, the third array convolution units and the fourth array convolution units differs from a one by one hardware convolution neural network unit, and wherein the building block is further executed by the neural network processor to perform max-pooling operations, such that the max-pooling operations are performed only after convolution operations.
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