| CPC G06F 9/4881 (2013.01) [G06F 9/30101 (2013.01); G06F 9/4812 (2013.01); G06F 9/546 (2013.01)] | 20 Claims | 

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               1. A processing system comprising: 
            a plurality of processors independently executing instructions; and 
                a plurality of registers, wherein each processor is associated with a corresponding register from the plurality of registers, each register including a set of first register bits corresponding to each of the plurality of processors; 
                wherein each register of the plurality of registers is configured to respectively set the first set of register bits for other processors except the corresponding processor; 
                wherein each processor of the plurality of processors is configured to write the first set of register bits to indicate event requests for the other processors in the corresponding register; 
                wherein each register of the plurality of registers is further configured to respectively set a second set of register bits for the other processors except the corresponding processor; 
                wherein each processor of the plurality of processors is further configured to enable the other processors by writing the second set of register bits in the corresponding register; 
                wherein each processor of the plurality of processors is further configured to read the first set of register bits of the corresponding register to acquire the event requests from the other processors; and 
                wherein each processor of the plurality of processors is further configured to query an inter-processor storage area for information related to the event requests before executing the event requests and after acquiring the event requests from the other processors. 
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