US 12,260,221 B2
Circuitry and method for instruction execution in dependence upon trigger conditions
Mbou Eyole, Soham (GB); Giacomo Gabrielli, Cambridge (GB); and Balaji Venu, Cambridge (GB)
Assigned to Arm Limited, Cambridge (GB)
Appl. No. 18/261,966
Filed by Arm Limited, Cambridge (GB)
PCT Filed Jan. 19, 2022, PCT No. PCT/GB2022/050149
§ 371(c)(1), (2) Date Jul. 18, 2023,
PCT Pub. No. WO2022/162344, PCT Pub. Date Aug. 4, 2022.
Claims priority of application No. 2101152 (GB), filed on Jan. 28, 2021.
Prior Publication US 2024/0220269 A1, Jul. 4, 2024
Int. Cl. G06F 9/38 (2018.01)
CPC G06F 9/3853 (2013.01) [G06F 9/38 (2013.01); G06F 9/3858 (2023.08)] 17 Claims
OG exemplary drawing
 
1. Circuitry comprising:
processing circuitry configured to execute program instructions in dependence upon respective trigger conditions matching a current trigger state and to set a next trigger state in response to program instruction execution; the processing circuitry comprising:
instruction storage configured to selectively provide a group of two or more program instructions for execution in parallel; and
trigger circuitry responsive to the generation of a trigger state by execution of program instructions and to a trigger condition associated with a given group of program instructions, to control the instruction storage to provide program instructions of the given group of program instructions for execution,
wherein the instruction storage comprises at least two instruction queues each configured to provide a group of program instructions for execution, the instruction queues comprising a first instruction queue configured to provide a group of up to n program instructions for execution in parallel and a second instruction queue configured to provide a group of up to m program instructions in parallel for execution, where m is not equal to n.