US 12,260,219 B2
Multiple instruction set architectures on a processing device
Duc Bui, Grand Prairie, TX (US); Timothy D. Anderson, University Park, TX (US); and Paul Gauvreau, Richardson, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jul. 20, 2023, as Appl. No. 18/355,939.
Claims priority of provisional application 63/393,029, filed on Jul. 28, 2022.
Prior Publication US 2024/0036866 A1, Feb. 1, 2024
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/30145 (2013.01) [G06F 9/3802 (2013.01); G06F 9/3836 (2013.01)] 21 Claims
OG exemplary drawing
 
1. Processing circuitry comprising:
first decoder circuitry;
second decoder circuitry;
instruction fetch circuitry configured to fetch instructions from memory;
instruction dispatch circuitry coupled with the instruction fetch circuitry, the first decoder circuitry, and the second decoder circuitry, and configured to:
route instructions associated with a first instruction set architecture to the first decoder circuitry; and
route instructions associated with a second instruction set architecture to the second decoder circuitry.