US 12,260,213 B2
Systems, methods, and apparatuses for matrix add, subtract, and multiply
Robert Valentine, Kiryat Tivon (IL); Dan Baum, Haifa (IL); Zeev Sperber, Zichron Yaakov (IL); Jesus Corbal, Barcelona (ES); Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US); Bret L. Toll, Hillsboro, OR (US); Mark J. Charney, Lexington, MA (US); Barukh Ziv, Haifa (IL); Alexander Heinecke, San Jose, CA (US); Milind Girkar, Sunnyvale, CA (US); and Simon Rubanovich, Haifa (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 10, 2021, as Appl. No. 17/548,214.
Application 17/548,214 is a continuation of application No. 16/474,507, granted, now 11,200,055, previously published as PCT/US2017/040540, filed on Jul. 1, 2017.
Claims priority of provisional application 62/473,732, filed on Mar. 20, 2017.
Prior Publication US 2022/0171623 A1, Jun. 2, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 7/485 (2006.01); G06F 7/487 (2006.01); G06F 7/76 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 17/16 (2006.01)
CPC G06F 9/30036 (2013.01) [G06F 7/485 (2013.01); G06F 7/4876 (2013.01); G06F 7/762 (2013.01); G06F 9/3001 (2013.01); G06F 9/30032 (2013.01); G06F 9/30038 (2023.08); G06F 9/30043 (2013.01); G06F 9/30109 (2013.01); G06F 9/30112 (2013.01); G06F 9/30134 (2013.01); G06F 9/30145 (2013.01); G06F 9/30149 (2013.01); G06F 9/3016 (2013.01); G06F 9/30185 (2013.01); G06F 9/30196 (2013.01); G06F 9/3818 (2013.01); G06F 9/3836 (2013.01); G06F 17/16 (2013.01); G06F 2212/454 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A processor comprising:
decode circuitry to decode an instruction having fields for an opcode, a first source matrix operand identifier, a second source matrix operand identifier, and a destination matrix operand identifier, wherein each of the first source matrix operand, the second source matrix operand, and the destination matrix operand corresponds to a two-dimensional matrix of values; and
execution circuitry to execute the decoded instruction to, for each data element position of the identified first source matrix operand:
multiply a first data value at that data element position by a second data value at a corresponding data element position of the identified second source matrix operand, and
store a result of the multiplication into a corresponding data element position of the identified destination matrix operand;
wherein a fault is generated when the first source matrix operand has a different number of data elements than the second source matrix operand.