US 12,260,199 B2
Merging skip-buffers in a reconfigurable dataflow processor
Fei Wang, Palo Alto, CA (US); David Alan Koeplinger, Egg Harbor, NJ (US); Kevin Brown, Palo Alto, CA (US); and Weiwei Chen, Palo Alto, CA (US)
Assigned to SambaNova Systems, Inc., Palo Alto, CA (US)
Filed by SambaNova Systems, Inc., Palo Alto, CA (US)
Filed on Mar. 27, 2023, as Appl. No. 18/126,610.
Claims priority of provisional application 63/324,500, filed on Mar. 28, 2022.
Prior Publication US 2023/0305823 A1, Sep. 28, 2023
Int. Cl. G06F 8/41 (2018.01)
CPC G06F 8/45 (2013.01) [G06F 8/4434 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A system in a reconfigurable dataflow processor, the system comprising:
a host computer comprising a processor and an optimization module configured to conduct a method comprising:
connecting a plurality of tensor consumers to their corresponding tensor producers via skip-buffers to produce a plurality of skip-buffers;
determining that at least one skip-buffer of the plurality of skip-buffers corresponding to a first set of tensor consumers and at least one skip-buffer of the plurality of skip-buffers corresponding to a second set of tensor consumers, are compatible to wholly or partially merge to produce mergeable skip-buffers; and
merging, wholly or partially, the mergeable skip-buffers to produce a merged skip-buffer having a minimal buffer depth.