| CPC G06F 30/392 (2020.01) [G06F 30/398 (2020.01); G06F 2111/04 (2020.01); G06F 2111/20 (2020.01)] | 20 Claims |
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1. A system comprising:
a memory storing a cell library,
wherein the cell library includes sets of cells with all cells in a set of cells having different combinations of cell boundary isolation structures associated with different delay values, and with each cell in each set having opposite ends and, at the opposite ends, two cell boundary isolation structures of at least three different types of possible cell boundary isolation structures,
wherein the memory further stores a layout for a logic circuit,
wherein the layout comprises multiple cells selected from the cell library to represent the logic circuit, and
wherein the memory further stores timing constraints for the logic circuit; and
a processor in communication with the memory and generating an updated layout by replacing a cell of the multiple cells in the layout with a replacement cell from a same set of cells in the cell library, wherein the replacement cell has a different combination of the cell boundary isolation structures than the cell to facilitate fixing of a violation of a timing constraint.
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