US 12,260,160 B2
Fabricated layout correlation
Adam Kimura, Lewis Center, OH (US); Rohan Prabhu, Dublin, OH (US); and Noah Mun, Columbus, OH (US)
Assigned to BATTELLE MEMORIAL INSTITUTE, Columbus, OH (US)
Filed by Battelle Memorial Institute, Columbus, OH (US)
Filed on Jan. 9, 2024, as Appl. No. 18/408,018.
Application 18/408,018 is a continuation of application No. 17/545,572, filed on Dec. 8, 2021, granted, now 11,907,627.
Claims priority of provisional application 63/125,426, filed on Dec. 15, 2020.
Prior Publication US 2024/0249050 A1, Jul. 25, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/327 (2020.01); G06F 30/27 (2020.01); G06F 30/3308 (2020.01); G06F 30/333 (2020.01); G06F 30/367 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06N 3/08 (2023.01); G06F 119/18 (2020.01); G06T 7/00 (2017.01)
CPC G06F 30/327 (2020.01) [G06F 30/333 (2020.01); G06F 30/392 (2020.01); G06N 3/08 (2013.01); G06F 30/27 (2020.01); G06F 30/3308 (2020.01); G06F 30/367 (2020.01); G06F 30/398 (2020.01); G06F 2119/18 (2020.01); G06T 7/0006 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) assessment device for assessing an IC-under-test, the IC assessment device comprising:
an electronic processor; and
a non-transitory storage medium storing:
a library of as-fabricated standard cell layout renderings constructed using at least one reference layout image acquired of a reference IC; and
instructions readable and executable by the electronic processor to perform an IC assessment method including identifying instantiated standard cells and their placements in a layout image of the IC-under-test by matching the instantiated standard cells with corresponding as-fabricated standard cell layout renderings retrieved from the library of as-fabricated standard cell layout renderings.