US 12,260,159 B2
System for collaborative hardware RTL logic timing debug in integrated circuit designs
Arun Joseph, Kadugodi (IN); Wolfgang Roesner, Austin, TX (US); Shashidhar Reddy, Bangalore (IN); Sampath Goud Baddam, Ramannager (IN); Anthony Saporito, Highland, NY (US); and Matthias Klein, Poughkeepsie, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Jan. 3, 2022, as Appl. No. 17/567,598.
Prior Publication US 2023/0214564 A1, Jul. 6, 2023
Int. Cl. G06F 30/327 (2020.01); G06F 111/02 (2020.01); G06F 119/12 (2020.01)
CPC G06F 30/327 (2020.01) [G06F 2111/02 (2020.01); G06F 2119/12 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method for identifying flaws in an integrated circuit, the method comprising:
selecting from a list of a plurality of timing issues in an integrated circuit, where each timing issue on the list is represented by one or more VHDL code lines, a particular timing issue to investigate;
next tracing back the one or more VHDL code lines, corresponding to the selected particular timing issue to investigate, to one or more physical design VHDL (PD-VHDL) code lines;
next logically navigating across the one or more PD-VHDL code lines, corresponding to the selected particular timing issue to investigate, to one or more corresponding normalized VHDL (NVDHL) code lines; and
next tracing back the one or more corresponding NVDHL code lines to one or more short-hand VHDL (SVHDL) code lines to identify one or more code lines, written by a code designer, responsible for the particular timing issue being investigated.