US 12,260,130 B2
Memory device for computing in-memory
Hang-Ting Lue, Hsinchu County (TW); Tzu-Hsuan Hsu, Chiayi County (TW); Teng-Hao Yeh, Hsinchu County (TW); Chih-Chang Hsieh, Hsinchu (TW); Chun-Hsiung Hung, Hsin-Chu (TW); and Yung-Chun Li, New Taipei (TW)
Assigned to MACRONIX International Co., Ltd., Hsinchu (TW)
Filed by MACRONIX International Co., Ltd., Hsinchu (TW)
Filed on Jan. 31, 2023, as Appl. No. 18/161,900.
Claims priority of provisional application 63/388,647, filed on Jul. 13, 2022.
Prior Publication US 2024/0028211 A1, Jan. 25, 2024
Int. Cl. G06F 17/16 (2006.01); G06F 3/06 (2006.01); G06F 7/49 (2006.01); G06N 3/00 (2023.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01); G11C 7/18 (2006.01); G11C 8/14 (2006.01); G11C 16/04 (2006.01); G11C 16/24 (2006.01); G11C 16/28 (2006.01); G11C 27/00 (2006.01)
CPC G06F 3/0679 (2013.01) [G06F 7/49 (2013.01); G06F 17/16 (2013.01); G06N 3/00 (2013.01); G11C 7/062 (2013.01); G11C 7/1006 (2013.01); G11C 7/18 (2013.01); G11C 8/14 (2013.01); G11C 16/0466 (2013.01); G11C 16/24 (2013.01); G11C 16/28 (2013.01); G11C 27/005 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device for computing in-memory, comprising:
a memory array comprising a plurality of first pairs of memory cells and a plurality of second pairs of memory cells, wherein each of the plurality of first pairs of memory cells comprises a first memory cell set coupled to a first global bit line and a second memory cell set coupled to a second global bit line, and each of the plurality of second pairs of memory cells comprises a third memory cell set coupled to the first global bit line and a fourth memory cell set coupled to the second global bit line;
a plurality of input word line pairs, wherein each of the plurality of input word line pairs comprises a first input word line and a second input word line, the first input word line is coupled to the first memory cell set and the second memory cell set, and the second input word line is coupled to the third memory cell set and the fourth memory cell sets; and
a signal processing circuit coupled to the first global bit line and the second global bit line.