US 12,260,119 B2
Memory system including multiple cores and method of operating the memory system
Hyun Woo Bae, Gyeonggi-do (KR); and Sang Yong Lee, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Dec. 15, 2022, as Appl. No. 18/081,688.
Claims priority of application No. 10-2022-0081479 (KR), filed on Jul. 1, 2022.
Prior Publication US 2024/0004578 A1, Jan. 4, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0656 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0679 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory system comprising:
a nonvolatile memory area;
a buffer memory area temporarily storing data; and
a plurality of cores configured to store, in the nonvolatile memory area, the data stored in the buffer memory area in response to an interrupt signal,
wherein each of the plurality of cores outputs the interrupt signal indicating that a sudden power off is sensed to remaining cores.