US 12,260,118 B2
Deterministic near-compute memory for deterministic processor and enhanced data movement between memory units and processing units
Dinesh Maheshwari, Fremont, CA (US)
Assigned to Groq, Inc., Mountain View, CA (US)
Filed by Groq, Inc., Mountain View, CA (US)
Filed on Dec. 12, 2022, as Appl. No. 18/079,722.
Application 18/079,722 is a continuation of application No. PCT/US2021/037488, filed on Jun. 15, 2021.
Claims priority of provisional application 63/047,800, filed on Jul. 2, 2020.
Claims priority of provisional application 63/039,982, filed on Jun. 16, 2020.
Prior Publication US 2023/0115494 A1, Apr. 13, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0656 (2013.01) [G06F 3/061 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A deterministic apparatus comprising:
a deterministic near-compute memory communicatively coupled with and proximate to a deterministic processor, the deterministic near-compute memory comprising a plurality of data banks having a global memory address space, a control bus, a data input bus, and a data output bus for each data bank; and
the deterministic processor configured to initiate, via the control bus, retrieval of a set of data from the plurality of data banks, the retrieved set of data comprising at least one row of a selected one of the data banks passed via the data output bus onto a plurality of stream registers of the deterministic processor,
wherein at least one memory bank of the deterministic near-compute memory is a low random transaction rate (RTR) dynamic random-access memory (DRAM).