US 12,260,114 B2
Techniques for priority information
Luca Porzio, Casalnuovo (IT); Gianluca Coppola, Liveri (IT); Ryan Laity, Boise, ID (US); and Christopher Joseph Bueb, Folsom, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 16, 2022, as Appl. No. 17/888,982.
Prior Publication US 2024/0061605 A1, Feb. 22, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system, comprising:
one or more memory devices; and
processing circuitry associated with the one or more memory devices and configured to cause the memory system to:
receive, at the memory system, an indication that data is critical to operating the memory system, the indication comprising a size of the data that is critical to operating the memory system;
receive the data that is critical to operating the memory system based at least in part on the indication;
select one or more parameters to provide a reliability of a storage of the data into the one or more memory devices of the memory system based at least in part on receiving the indication and receiving the data; and
program the data into the one or more memory devices of the memory system using the one or more parameters based at least in part on selecting the one or more parameters.