US 12,260,110 B2
Managing trim commands in a memory sub-system
Yueh-Hung Chen, Sunnyvale, CA (US); Fangfang Zhu, San Jose, CA (US); Horia Simionescu, Foster City, CA (US); Chih-Kuo Kao, Fremont, CA (US); and Jiangli Zhu, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 5, 2023, as Appl. No. 18/529,868.
Application 18/529,868 is a continuation of application No. 17/462,629, filed on Aug. 31, 2021, granted, now 11,868,642.
Prior Publication US 2024/0103752 A1, Mar. 28, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0652 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising: a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
identifying a group of memory cells corresponding to a first range of logical block addresses (LBAs);
receiving a memory access command with respect to the group of memory cells;
responsive to determining that a data structure associated with the group of memory cells references a trim command, blocking the memory access command, wherein the trim command is directed to a second range of LBAs;
responsive to determining that the second range of LBAs corresponds to a number of management units (MUs) less than a maximum number of MUs included in the group of memory cells, performing, on the group of memory cells, a trim operation, wherein the maximum number of MUs included in the group of memory cells corresponds to the first range of LBAs;
responsive to determining that the data structure indicates a completion of the trim operation, performing a memory access operation specified by the memory access command.