| CPC G06F 3/064 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0652 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] | 20 Claims |

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1. An apparatus, comprising:
an array of memory cells;
a controller coupled to the array of memory cells, wherein the controller is configured to determine a source for read requests and to:
direct read requests for a first portion of data to a first block of single level memory cells in response to an amount of a second portion of data written to a second block of single level memory cells being less than a threshold amount; and
direct read requests for the first portion of data to a first block of a quad level memory cells in response to the amount of the second portion of data written to the second block of single level memory cells being at least the threshold amount.
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