US 12,260,100 B2
Data storage device and data processing method for arranging a write order of writing data based on a logical data order of reading the data
Chi-Hung Cheng, Taipei (TW)
Assigned to Silicon Motion, Inc., Hsinchu County (TW)
Filed by Silicon Motion, Inc., Hsinchu County (TW)
Filed on Jul. 25, 2023, as Appl. No. 18/226,246.
Claims priority of application No. 112115775 (TW), filed on Apr. 27, 2023.
Prior Publication US 2024/0361934 A1, Oct. 31, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/064 (2013.01) [G06F 3/0626 (2013.01); G06F 3/0658 (2013.01); G06F 3/0688 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A data storage device, comprising:
a memory device, comprising a plurality of memory dies, wherein each memory die comprises a plurality of planes, one of the planes of each memory die corresponds to one of a plurality of plane indices, and each plane comprises a plurality of memory blocks, each memory block comprises a plurality of pages, the memory blocks form a plurality of superblocks, each superblock comprises a predetermine number of the memory blocks and the predetermine number of the memory blocks are respectively in different planes of different memory dies; and
a memory controller, coupled to the memory device to access the memory device, wherein in response to a write command received from a host device, the memory controller performs a write operation to write predetermined data into the memory device, and in the write operation, the memory controller selects one from the superblocks as a first target superblock of the write operation and sequentially writes a plurality of portions of the predetermined data into the pages of the first target superblock in a cyclic manner among the memory dies according to an order of the plane indices,
wherein each memory die comprises at least a first plane and a second plane, in the write operation of the predetermined data, and corresponding write operations performed on a first page on the first plane of all memory dies of the first target superblock are earlier than corresponding write operations performed on a first page on the second plane of all memory dies of the first target superblock, and
wherein one of the superblocks corresponds to one of a plurality of superblock indices, and when a size of an available space of the first target superblock is smaller than or equal to a threshold, the memory controller selects another from the superblocks as a second target superblock of the write operation according to an order of the superblock indices and sequentially writes remaining portions of the predetermined data that have not been written in the memory device into the pages of the second target superblock in the cyclic manner among the memory dies according to the order of the plane indices.