US 12,260,098 B2
Memory channel disablement
Yang Lu, Boise, ID (US); Yu-Sheng Hsu, San Jose, CA (US); Kang-Yong Kim, Boise, ID (US); and Ke Wei Chan, Zhudong Township (TW)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 14, 2022, as Appl. No. 17/944,572.
Prior Publication US 2024/0086090 A1, Mar. 14, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0629 (2013.01) [G06F 3/061 (2013.01); G06F 3/0673 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a plurality of memory devices comprising memory chips having memory dice; and
a memory controller coupled to the plurality of memory devices via memory channels, wherein each memory device of the plurality of memory devices is a multi-channel memory device comprising at least two memory chips located therein that are coupled to different respective first and second memory channels, and wherein the memory controller is configured to:
selectively disable one of the first memory channel or the second memory channel of a particular memory device due to a determination that a memory die within a memory chip associated with the one of the first memory channel or the second memory channel does not satisfy a reliability criterion; and
subsequent to disabling the one of the first memory channel or the second memory channel, perform a memory operation via the other of the first memory channel or the second memory channel.