US 12,260,096 B2
Method of reducing Vpass disturb in 3D nand systems
Jie Yuan, Hubei (CN); Ying Cui, Hubei (CN); Yuanyuan Min, Hubei (CN); YaLi Song, Hubei (CN); and HongTao Liu, Hubei (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Hubei (CN)
Filed on Nov. 10, 2022, as Appl. No. 18/054,470.
Prior Publication US 2024/0160356 A1, May 16, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/0629 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for programming a memory device having a plurality of memory cells, the method comprising:
performing a programming operation on one of the memory cells, wherein the one of the memory cells is controlled by a selected word line of a plurality of word lines, wherein the plurality of word lines comprises:
a first unselected word line adjacent to the selected word line;
a first plurality of unselected word lines adjacent to the first unselected word line, wherein the first plurality of unselected word lines are adjacent to each others and on one side of the selected word line; and
a second plurality of unselected word lines adjacent to the first plurality of unselected word lines, wherein the second plurality of unselected word lines are adjacent to each other and on one side of the selected word line,
wherein performing the programming operation comprises:
applying a programming voltage signal to the selected word line to program the one of the memory cells into a target state;
applying a first pass voltage to the first plurality of unselected word lines; and
applying a second pass voltage to the second plurality of unselected word lines, wherein the first pass voltage is different from the second pass voltage.