US 12,260,095 B2
Memory device and method of operating the same
Ka Young Cho, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Nov. 23, 2022, as Appl. No. 17/993,437.
Claims priority of application No. 10-2022-0073486 (KR), filed on Jun. 16, 2022.
Prior Publication US 2023/0409208 A1, Dec. 21, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/0653 (2013.01); G06F 3/0679 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory cell array including a plurality of memory cells connected to a plurality of word lines;
a peripheral circuit configured to perform a plurality of program loops each including a program operation on selected memory cells among the plurality of memory cells and a verify operation on the program operation;
a compensation operation controller configured to determine a compensation value for a plurality of verify voltages according to a progress degree of the program operation and a target program state based on compensation information during the verify operation; and
a verify operation controller configured to control the peripheral circuit to perform the verify operation on the selected memory cells among the plurality of memory cells based on the plurality of verify voltages to which the determined compensation value is applied,
wherein the compensation operation controller is configured to:
change the compensation value whenever program loops corresponding to a step loop are performed from a predetermined loop among the plurality of program loops, and
apply the changed compensation value to the plurality of verify voltages.