US 12,260,092 B2
Systems and methods for generating logical-to-physical tables for wear-leveling
Rajesh N. Gupta, Bengaluru (IN)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 6, 2022, as Appl. No. 17/903,772.
Application 17/903,772 is a continuation of application No. 16/727,196, filed on Dec. 26, 2019, granted, now 11,442,631, issued on Sep. 13, 2022.
Prior Publication US 2023/0004307 A1, Jan. 5, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 12/1009 (2016.01)
CPC G06F 3/0616 (2013.01) [G06F 3/0635 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 12/1009 (2013.01); G06F 2212/1036 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
determining, via a long short-term memory deep-learning recurrent neural network executed on a memory controller, a first assignment that causes a first logical address to correspond to a first physical address for a first memory portion;
determining, via the long short-term memory deep-learning recurrent neural network executed on the memory controller, a first memory access latency associated with the first assignment based on a first set of memory access patterns;
generating, via the long short-term memory deep-learning recurrent neural network executed on the memory controller, a second assignment that causes the first logical address to correspond to a second physical address for a second memory portion and a third assignment that causes the first logical address to correspond to a third physical address for a third memory portion; and
selecting, via the long short-term memory deep-learning recurrent neural network executed on the memory controller, the second assignment or the third assignment based on the first memory access latency, a second memory access latency associated with the second assignment based on a second set of memory access patterns, and a third memory access latency associated with the third assignment based on a third set of memory access patterns.