US 12,260,088 B2
Commanded device states for a memory system
Marco Onorato, Villasanta (IT); Luca Porzio, Casalnuovo (IT); Roberto Izzi, Caserta (IT); and Nadav Grosz, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 17, 2022, as Appl. No. 17/663,722.
Prior Publication US 2023/0376205 A1, Nov. 23, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0611 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0631 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 2212/7206 (2013.01)] 26 Claims
OG exemplary drawing
 
1. A memory system, comprising:
one or more memory devices; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
receive, from a host system coupled with the memory system, a first command to operate the memory system in a first target device state of a plurality of device states of the memory system, wherein each device state of the plurality of device states is configured at the memory system with a correspondence to a respective allocation of resources for operations of the memory system;
set a first combination of multiple parameters of the memory system associated with the respective allocation of resources corresponding to the first target device state based at least in part on receiving the first command to operate the memory system in the first target device state;
transmit, in response to the first command, a first indication that the memory system has entered the first target device state based at least in part on setting the first combination of multiple parameters;
perform first operations of the memory system in accordance with the respective allocation of resources corresponding to the first target device state based at least in part on setting the first combination of multiple parameters;
receive, from the host system, a second command to transition from operating the memory system in the first target device state to a second target device state of the plurality of device states after performing the first operations of the memory system;
set a second combination of multiple parameters of the memory system associated with the respective allocation of resources corresponding to the second target device state based at least in part on receiving the second command to operate the memory system in the second target device state;
transmit, in response to the second command, a second indication that the memory system has entered the second target device state based at least in part on setting the second combination of multiple parameters; and
perform second operations of the memory system in accordance with the respective allocation of resources corresponding to the second target device state based at least in part on setting the second combination of multiple parameters.