US 12,260,087 B2
Output driving and input on-die termination mechanism capable of supporting different requirements of different flash memory specification standards
Zih-Yang Wong, Hsinchu (TW)
Assigned to Silicon Motion, Inc., Hsinchu County (TW)
Filed by Silicon Motion, Inc., Hsinchu County (TW)
Filed on Mar. 16, 2023, as Appl. No. 18/122,695.
Prior Publication US 2024/0311007 A1, Sep. 19, 2024
Int. Cl. H04L 25/02 (2006.01); G06F 3/06 (2006.01); H03K 19/00 (2006.01)
CPC G06F 3/061 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An input/output (I/O) interface circuit, disposed within a flash memory controller and to be coupled to a flash memory externally coupled to the flash memory controller through an I/O signal port of the flash memory controller, comprising:
a transmission and on-die termination circuit, operating as either an output driving stage circuit or an input on-die termination stage circuit; and
a controlling circuit, coupled to the transmission and on-die termination circuit, for receiving at least one control signal sent from a processor circuit and using the at least one control signal to control the transmission and on-die termination circuit as the output driving stage circuit transferring and driving a transmission signal, sent from the processor circuit of the flash memory controller, to the flash memory through the I/O signal port and to control the transmission and on-die termination circuit as the input on-die termination stage circuit generating and providing a matching termination resistance for the I/O signal port;
wherein the transmission and on-die termination circuit comprises:
a plurality of first multiplexers, a corresponding first multiplexer having a first input coupled to a first control signal sent from the processor circuit of the flash memory controller, a second input coupled to a second control signal sent from the processor circuit, a control input coupled to a setting signal sent from the processor circuit, and an output, the corresponding first multiplexer being arranged for selecting the first control signal or the second control signal as an output signal according to the setting signal;
a plurality of second multiplexers, a corresponding second multiplexer having a first input coupled to a third control signal sent from the processor circuit of the flash memory controller, a second input coupled to a fourth control signal sent from the processor circuit, a control input coupled to the setting signal sent from the processor circuit, and an output, the corresponding second multiplexer being arranged for selecting the third control signal or the fourth control signal as an output signal of the corresponding second multiplexer according to the setting signal; and
a plurality of impedance circuits, a corresponding impedance circuit comprising:
a corresponding first switch unit, coupled between a supply reference voltage level and a corresponding first resistor unit, a state of the corresponding first switch unit being controlled by the output signal of the corresponding first multiplexer;
the corresponding first resistor unit having a corresponding first resistance, coupled between the corresponding first switch unit and the I/O signal port;
a corresponding second switch unit, coupled between a ground level and a corresponding second resistor unit, a state of the corresponding second switch unit being controlled by the output signal of the corresponding second multiplexer; and
the corresponding second resistor unit having a corresponding second resistance, coupled between the corresponding second switch unit and the I/O signal port;
wherein the corresponding first switch unit and the corresponding first resistor unit are connected in series between the supply reference voltage level and the I/O signal port when the state of the corresponding first switch unit is closed; the corresponding second switch unit and the corresponding second resistor unit are connected in series between the ground level and the I/O signal port when the state of the corresponding second switch unit is closed.