US 12,260,046 B2
Driving circuit, display device including the same, and electronic device including display device
Jun Young Ko, Yongin-si (KR); Tae Hyeon Yang, Yongin-si (KR); Han Su Cho, Yongin-si (KR); Tae Joon Kim, Yongin-si (KR); Hyun Wook Cho, Yongin-si (KR); and Jae Woo Choi, Yongin-si (KR)
Assigned to Samsung Display Co., Ltd., Yongin-si (KR)
Filed by Samsung Display Co., LTD., Yongin-si (KR)
Filed on Jun. 26, 2023, as Appl. No. 18/341,729.
Claims priority of application No. 10-2022-0139660 (KR), filed on Oct. 26, 2022.
Prior Publication US 2024/0143114 A1, May 2, 2024
Int. Cl. G06F 3/041 (2006.01); G09G 3/3275 (2016.01)
CPC G06F 3/04184 (2019.05) [G06F 3/04164 (2019.05); G09G 3/3275 (2013.01); G09G 2310/08 (2013.01); G09G 2354/00 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A driving circuit comprising:
a display driver configured to generate a horizontal synchronization signal and a vertical synchronization signal according to a first clock signal of a first oscillator:
a sensor driver configured to generate a touch signal according to a second clock signal of a second oscillator; and
a determination circuit configured to detect a cycle of at least one of the horizontal synchronization signal or the vertical synchronization signal according to the second clock signal, and output a detection signal when the cycle is out of a range,
wherein the determination circuit is a part of the display driver or the sensor driver, and
wherein to detect the cycle of the at least one of the horizontal synchronization signal or the vertical synchronization signal according to the second clock signal, the determination circuit is configured to count a number of times that the second clock signal overlaps with at least one of a high level section or a low level section of the horizontal synchronization signal or the vertical synchronization signal,
wherein the determination circuit is configured to detect the cycle of the horizontal synchronization signal according to a first count value of the second clock signal included in the high level section of the horizontal synchronization signal, and a second count value of the second clock signal included in the low level section of the horizontal synchronization signal,
wherein the determination circuit is configured to output the detection signal when the first count value or the second count value is out of the range.