US 12,259,973 B2
Systems and methods for flush plus reload cache side-channel attack mitigation
Ishwar Agarwal, Redmond, WA (US); Bharat Pillilli, El Dorado Hills, CA (US); and Vishal Soni, Redmond, WA (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Jun. 13, 2022, as Appl. No. 17/838,446.
Claims priority of provisional application 63/345,683, filed on May 25, 2022.
Prior Publication US 2023/0385410 A1, Nov. 30, 2023
Int. Cl. G06F 21/55 (2013.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 12/0891 (2016.01); G06F 21/54 (2013.01); G06F 21/79 (2013.01)
CPC G06F 21/556 (2013.01) [G06F 9/30047 (2013.01); G06F 9/3858 (2023.08); G06F 21/54 (2013.01); G06F 21/552 (2013.01); G06F 21/79 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processor comprising:
an instruction cache;
a fetch unit to fetch instructions and store a set of fetched instructions in the instruction cache, wherein the set of fetched instructions includes a plurality of cache flush instructions, wherein each of the plurality of cache flush instructions, if executed by the processor, is configured to flush at least one cache line from the at least one cache associated with the processor;
a microcode read-only memory (ROM) to store micro-instructions, including a first set of micro-instructions for performing the cache flush instruction;
a microcode patch random-access memory (RAM) to supply a second set of micro-instructions corresponding to a cache write back instruction;
a decoding unit to receive the second set of micro-instructions from the microcode patch RAM, instead of the first set of micro-instructions from the microcode ROM, even when an incoming instruction received by the instruction cache comprises the cache flush instruction; and
an execution unit to execute the second set of micro-instructions corresponding to the cache write back instruction, resulting in an automatic mapping of the plurality of cache flush instructions into a respective cache write back instruction.