US 12,259,841 B2
Passive clock synchronization for timing
Ian Kenneth Coolidge, San Diego, CA (US); and Shahin Valoth, Santa Clara, CA (US)
Assigned to Google LLC, Mountain View, CA (US)
Filed by Google LLC, Mountain View, CA (US)
Filed on Aug. 23, 2023, as Appl. No. 18/237,171.
Prior Publication US 2025/0068581 A1, Feb. 27, 2025
Int. Cl. G06F 13/42 (2006.01)
CPC G06F 13/423 (2013.01) 18 Claims
OG exemplary drawing
 
1. A method for synchronization in a multi-interface card environment, comprising:
transmitting, by a computing device, a synchronization message to a first interface card through a passive splitter, wherein the passive splitter is further coupled to at least one second interface card;
receiving, by the computing device, a delay request transmitted by the first interface card through the passive splitter;
transmitting, by the computing device, a delay response to the first interface card through the passive splitter;
listening, by the second interface card, to the delay request and the delay response through the passive splitter; and
synchronizing, by the second interface card, to at least one of the computing device or the first interface card based on the listening.