US 12,259,839 B2
Multi-chip interconnection system based on PCIE buses
Shufan Guo, Shenzhen (CN); Yonghang Wu, Shenzhen (CN); Kunyan Cai, Shenzhen (CN); and Shifeng Li, Shenzhen (CN)
Assigned to ZTE CORPORATION, Shenzhen (CN)
Appl. No. 17/771,549
Filed by ZTE Corporation, Shenzhen (CN)
PCT Filed Oct. 20, 2020, PCT No. PCT/CN2020/122248
§ 371(c)(1), (2) Date Apr. 25, 2022,
PCT Pub. No. WO2021/082990, PCT Pub. Date May 6, 2021.
Claims priority of application No. 201911056191.2 (CN), filed on Oct. 31, 2019.
Prior Publication US 2022/0365898 A1, Nov. 17, 2022
Int. Cl. G06F 13/36 (2006.01); G06F 13/42 (2006.01)
CPC G06F 13/4221 (2013.01) [G06F 2213/0026 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A multi-chip interconnection system based on Peripheral Component Interconnect Express (PCIE) buses, comprising:
N accelerators, M processors, and M PCIE buses connecting the M processors with the N accelerators, N and M being positive integers, and M being greater than N;
wherein each accelerator of the N accelerators comprises at least two endpoints, and each processor of the M processors comprises one root complex, wherein the at least two endpoints comprised in the each accelerator are connected with at least two root complexes of at least two processors in a one-to-one correspondence respectively by means of at least two PCIE buses among the M PCIE buses, so that the at least two endpoints comprised in the each accelerator are connected to the at least two processors by means of different PCIE buses;
wherein the M processors comprise a first processor, wherein the root complex comprised in the first processor is connected to an endpoint comprised in one accelerator of the N accelerators by means of a first PCIE bus; the first processor is configured to convert a read and/or write access request into an access address of a domain of the first PCIE bus; in a case where the converted access address of the domain of the first PCIE bus falls into a domain space of a second processor, convert the access address of the domain of the first PCIE bus into an access address of a domain space of the second processor, so that the first processor accesses data of the second processor.