US 12,259,838 B2
Memory controller, method of operating memory controller and storage device
Jong Hoon Kim, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-Do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jan. 11, 2023, as Appl. No. 18/153,022.
Application 18/153,022 is a continuation of application No. 17/220,986, filed on Apr. 2, 2021, granted, now 11,561,919, issued on Jan. 24, 2023.
Claims priority of application No. 10-2020-0100460 (KR), filed on Aug. 11, 2020.
Prior Publication US 2023/0169027 A1, Jun. 1, 2023
Int. Cl. G06F 13/40 (2006.01); G06F 13/38 (2006.01); G06F 13/42 (2006.01)
CPC G06F 13/4022 (2013.01) [G06F 13/4291 (2013.01); G06F 13/385 (2013.01); G06F 2213/0026 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory controller comprising:
a physical layer (PHY) module including a first PHY terminal and a second PHY terminal connected to a plurality of pins included in a device connector according to a type of the device connector;
a media access layer (MAC) module including a first port including a first MAC terminal and a second MAC terminal different from each other, and a second port including a third MAC terminal, the second port being different from the first port; and
a switch configured to disable the third MAC terminal and form a first lane by connecting the first PHY terminal to the first MAC terminal and connecting the second PHY terminal to the second MAC terminal at a first time point,
the switch being configured to,
disable the second MAC terminal, form the first lane by connecting the first PHY terminal to the first MAC terminal, and
form a second lane by connecting the second PHY terminal to the third MAC terminal at a second time point different from the first time point, wherein
the first PHY terminal is connected to a first host single pin of a first host port and the second PHY terminal is connected to a second host single pin of the first host port at the first time point, and
the first PHY terminal is connected to the first host single pin of the first host port and the second PHY terminal is connected to a third host single pin of a second host port at the second time point.