US 12,259,835 B2
Disaggregation of computing devices using enhanced retimers with circuit switching
Debendra Das Sharma, Saratoga, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 21, 2021, as Appl. No. 17/353,416.
Claims priority of provisional application 63/114,443, filed on Nov. 16, 2020.
Prior Publication US 2021/0311895 A1, Oct. 7, 2021
Int. Cl. G06F 13/364 (2006.01); G06F 13/362 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01)
CPC G06F 13/364 (2013.01) [G06F 13/3625 (2013.01); G06F 13/4081 (2013.01); G06F 13/4221 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a retimer comprising:
retimer circuitry to forward data received on ingress lanes to egress lanes;
a plurality of ingress lanes;
a plurality of egress lanes;
multiplexer circuitry, wherein the multiplexer circuitry implements a respective multiplexer at each of the plurality of egress lanes, and each of the multiplexers at the egress lanes couple to the plurality of ingress lanes; and
a system management port to receive a control signal, wherein the control signal comprises connection settings to identify which ingress lanes in the plurality of ingress lanes are to be connected to which egress lanes in the plurality of egress lanes, wherein the control signal causes the multiplexer circuitry to couple the plurality of ingress lanes to the plurality of egress lanes based on the connection settings.