US 12,259,832 B2
Multi-socket network interface controller with consistent transaction ordering
Tzahi Oved, Ramat Gan (IL); Achiad Shochat, Rosh Pina (IL); Liran Liss, Misgav (IL); Noam Bloch, Bat Shlomo (IL); Aviv Heller, Rishon le Zion (IL); Idan Burstein, Akko (IL); Ariel Shahar, Jerusalem (IL); and Peter Paneah, Nesher (IL)
Assigned to Mellanox Technologies, Ltd, Yokneam (IL)
Filed by MELLANOX TECHNOLOGIES, LTD., Yokneam (IL)
Filed on Feb. 27, 2023, as Appl. No. 18/174,668.
Application 18/174,668 is a continuation of application No. 17/503,392, filed on Oct. 18, 2021, granted, now 11,620,245.
Claims priority of provisional application 63/186,124, filed on May 9, 2021.
Prior Publication US 2023/0214341 A1, Jul. 6, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/28 (2006.01); G06F 3/06 (2006.01)
CPC G06F 13/28 (2013.01) [G06F 3/061 (2013.01); G06F 3/0655 (2013.01); G06F 3/0673 (2013.01); G06F 2213/28 (2013.01)] 20 Claims
OG exemplary drawing
 
1. Computing apparatus, comprising:
a host computer, comprising multiple non-uniform memory access (NUMA) nodes, including at least first and second NUMA nodes, which respectively comprise first and second central processing units (CPUs), first and second local memories, and first and second host bus interfaces for connection to first and second peripheral component buses, respectively; and
a network interface controller (NIC), comprising:
a network port, for connection to a packet communication network;
first and second NIC bus interfaces, to communicate via the first and second peripheral component buses with the first and second host bus interfaces, respectively; and
packet processing logic, which is coupled between the network port and the first and second NIC bus interfaces and is to receive a definition of a memory region extending over respective first and second parts of the first and second local memories and to receive a memory mapping with respect to the memory region that is applicable to both the first and second local memories, and to apply the memory mapping in writing data to the memory region via both the first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions to the respective first and second parts of the first and second local memories in response to packets received through the network port.