US 12,259,827 B2
Systems and methods for address scrambling
Bhaswar Mitra, Santa Clara, CA (US); and Mark Birman, San Jose, CA (US)
Assigned to AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED, Singapore (SG)
Filed by Avago Technologies International Sales Pte. Limited, Singapore (SG)
Filed on Jan. 31, 2023, as Appl. No. 18/104,019.
Prior Publication US 2024/0256467 A1, Aug. 1, 2024
Int. Cl. G06F 12/00 (2006.01); G06F 12/02 (2006.01); G06F 12/14 (2006.01); G06F 13/00 (2006.01)
CPC G06F 12/1408 (2013.01) [G06F 12/0292 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A system, comprising:
memory configured to store a plurality of tables, each table of the plurality of tables having a plurality of entries, and each entry of the plurality of entries having a corresponding entry index;
a lookup circuit, coupled with the memory, the lookup circuit configured to provide a plurality of entry indexes for each table of the plurality of tables to an address circuit; and
the address circuit, comprising:
a first circuit comprising:
a plurality of entry scramblers, each entry scrambler of the plurality of entry scramblers having a scrambling technique; and
a first entry scrambler of the plurality of entry scramblers configured to:
receive, from the lookup circuit, a first entry index of a first table of the plurality of tables, the first entry index associated with a first entry of the first table; and
change, using the scrambling technique of the first entry scrambler, the first entry index from a first value to a second value;
the scrambling technique of the first entry scrambler comprises a cryptographic process of encryption to encrypt the first entry index;
a second circuit including a plurality of translators;
a first translator of the plurality of translators configured to:
receive, from the first entry scrambler, the second value of the first entry index; and
translate the second value of the first entry index to a first address within the memory, the first address within the memory corresponding to a first location of the first entry in the memory; and
a third circuit comprising:
a plurality of row scramblers, each row scrambler of the plurality of row scramblers having a scrambling technique configured in a first manner; and
a first row scrambler of the plurality of row scramblers configured to:
receive, from the first translator, the first address within the memory; and
change, using the scrambling technique of the first row scrambler, the first address within the memory to a second address within the memory.