US 12,259,825 B2
Concurrent support for multiple cache inclusivity schemes using low priority evict operations
Wesley Waylon Terpstra, San Mateo, CA (US); Richard Van, San Jose, CA (US); and Eric Andrew Gouldey, Fort Collins, CO (US)
Assigned to SiFive, Inc., Santa Clara, CA (US)
Filed by SiFive, Inc., San Mateo, CA (US)
Filed on Dec. 20, 2023, as Appl. No. 18/390,223.
Claims priority of provisional application 63/434,080, filed on Dec. 20, 2022.
Prior Publication US 2024/0202137 A1, Jun. 20, 2024
Int. Cl. G06F 12/121 (2016.01); G06F 12/0811 (2016.01); G06F 12/084 (2016.01)
CPC G06F 12/121 (2013.01) [G06F 12/084 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a first inner cache that is configured to transmit eviction messages having a lower priority than probe messages;
a second inner cache that is configured to transmit eviction messages having a higher priority than probe messages; and
a shared cache that is connected to the first inner cache and to the second inner cache as parts of a cache hierarchy, and configured to:
receive a first eviction message having the lower priority than probe messages from the first inner cache;
receive a second eviction message having the higher priority than probe messages from the second inner cache;
transmit a third eviction message, determined based on the first eviction message, having the lower priority than probe messages to a circuitry that is closer to memory in the cache hierarchy; and
transmit a fourth eviction message, determined based on the second eviction message, having the lower priority than probe messages to the circuitry that is closer to memory in the cache hierarchy.