US 12,259,820 B2
Processor-based system for allocating cache lines to a higher-level cache memory
Ramkumar Srinivasan, Bangalore (IN)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Apr. 2, 2024, as Appl. No. 18/624,301.
Application 18/624,301 is a continuation of application No. 18/169,852, filed on Feb. 15, 2023, granted, now 12,093,184.
Claims priority of provisional application 63/387,519, filed on Dec. 15, 2022.
Prior Publication US 2024/0248851 A1, Jul. 25, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/08 (2016.01); G06F 12/0891 (2016.01); G06F 12/0897 (2016.01); G06F 12/126 (2016.01)
CPC G06F 12/0897 (2013.01) [G06F 12/0891 (2013.01); G06F 12/126 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for allocating a cache line to a higher-level cache memory in response to an eviction request of a lower-level cache line in a lower-level cache memory, comprising:
determining whether the lower-level cache line is opportunistic;
determining, based on whether the lower-level cache line is opportunistic, whether a higher-level cache line of a plurality of higher-level cache lines in the higher-level cache memory has less or equal importance than the lower-level cache line; and
in response to the determining the higher-level cache line has less or equal importance than the lower-level cache line:
replacing the higher-level cache line in the higher-level cache memory with the lower-level cache line; and
associating whether the lower-level cache line is opportunistic with the higher-level cache line in the higher-level cache memory.