| CPC G06F 12/0877 (2013.01) [G06F 13/28 (2013.01); G06F 2212/60 (2013.01); G06F 2213/28 (2013.01)] | 19 Claims |
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1. A smart storage device, comprising:
a smart interface directly connected to a host device;
an accelerator circuit connected to the smart interface through a data bus conforming to a cache-coherent interconnect shared memory region cache protocol (cache protocol) and a cache-coherent interconnect memory pooling and expansion protocol (mem protocol), and configured to perform acceleration computation for data in an accelerator memory device in response to a computation command of the host device; and
a storage controller connected to the smart interface through a data bus conforming to a cache-coherent interconnect device discovery, configuration, and I/O operations protocol (IO protocol) and configured to control a data access operation for data in an accelerator memory device of a storage device in response to a data access command of the host device,
wherein the accelerator circuit is directly accessible to the storage device through an internal bus connected directly to the storage controller, while the accelerator circuit and the storage controller are each separately connected to the host device over the smart interface independent of the internal bus,
wherein the accelerator circuit transmits a data access request to the storage controller through the internal bus without intervention of the host device in response to the computation command and receives a first data corresponding to the data access request in a non-volatile memory device through the internal bus and stores the first data into the accelerator memory device,
wherein the internal bus is not directly connected to the host device.
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