US 12,259,816 B2
Composable infrastructure enabled by heterogeneous architecture, delivered by CXL based cached switch SOC
Shreyas Shah, San Jose, CA (US); George Apostol, Jr., Los Gatos, CA (US); Nagarajan Subramaniyan, San Jose, CA (US); Jack Regula, Durham, NC (US); and Jeffrey S. Earl, San Jose, CA (US)
Assigned to AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE., LIMITED, San Jose, CA (US)
Filed by AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED, San Jose, CA (US)
Filed on Jun. 28, 2022, as Appl. No. 17/809,475.
Claims priority of provisional application 63/223,045, filed on Jul. 18, 2021.
Prior Publication US 2023/0017643 A1, Jan. 19, 2023
Int. Cl. G06F 12/08 (2016.01); G06F 12/06 (2006.01); G06F 12/0815 (2016.01); G06F 12/0837 (2016.01); G06F 12/0862 (2016.01); G06F 12/0868 (2016.01); G06F 12/14 (2006.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); G06N 20/00 (2019.01)
CPC G06F 12/0868 (2013.01) [G06F 12/0646 (2013.01); G06F 12/0815 (2013.01); G06F 12/0837 (2013.01); G06F 12/0862 (2013.01); G06F 12/1466 (2013.01); G06F 13/1642 (2013.01); G06F 13/1668 (2013.01); G06F 13/1673 (2013.01); G06F 13/4022 (2013.01); G06F 13/4221 (2013.01); G06F 2213/0026 (2013.01); G06N 20/00 (2019.01)] 12 Claims
OG exemplary drawing
 
1. A system comprising:
a first server device comprising:
a first memory device; and
a first cache coherent switch on chip, communicatively coupled to the first memory device via a Compute Express Link (CXL) protocol; and
a second server device, communicatively coupled to the first server device via a data connection, the second server device comprising:
a second memory device; and
a second cache coherent switch on chip, communicatively coupled to the second memory device via the CXL protocol and communicatively coupled to the first cache coherent switch on chip by the data connection via the CXL protocol, wherein second cache coherent switch on chip is configured to:
determine that the second memory device is to be shared with the first server device;
generate an access key for the first server device to access the second memory device; and
provide, to the first server device via the data connection, the access key; and
wherein the first cache coherent switch is configured to communicate CXL protocol memory commands to the second cache coherent switch, each of the CXL protocol memory commands including an instruction and the access key for the first server device to access the second memory device.