US 12,259,813 B2
Controller for controlling non-volatile semiconductor memory and method of controlling non-volatile semiconductor memory
Kazuhiro Fukutomi, Tokyo (JP); Kenichiro Yoshii, Tokyo (JP); Shinichi Kanno, Tokyo (JP); and Shigehiro Asano, Tokyo (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Apr. 2, 2024, as Appl. No. 18/624,930.
Application 18/624,930 is a continuation of application No. 18/310,597, filed on May 2, 2023, granted, now 11,977,481.
Application 18/310,597 is a continuation of application No. 17/590,310, filed on Feb. 1, 2022, granted, now 11,675,697, issued on Jun. 13, 2023.
Application 17/590,310 is a continuation of application No. 16/995,029, filed on Aug. 17, 2020, granted, now 11,269,766, issued on Mar. 8, 2022.
Application 16/995,029 is a continuation of application No. 16/255,284, filed on Jan. 23, 2019, granted, now 10,783,072, issued on Sep. 22, 2020.
Application 16/255,284 is a continuation of application No. 15/901,443, filed on Feb. 21, 2018, granted, now 10,229,053, issued on Mar. 12, 2019.
Application 15/901,443 is a continuation of application No. 15/530,151, filed on Dec. 8, 2016, granted, now 9,940,233, issued on Apr. 10, 2018.
Application 15/530,151 is a continuation of application No. 13/933,804, filed on Jul. 2, 2013, granted, now 9,690,691, issued on Jun. 27, 2017.
Application 13/933,804 is a continuation of application No. 12/883,796, filed on Sep. 16, 2010, granted, now 8,495,336, issued on Jul. 23, 2013.
Claims priority of application No. 2010-063191 (JP), filed on Mar. 18, 2010.
Prior Publication US 2024/0256442 A1, Aug. 1, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/02 (2006.01); G06F 3/06 (2006.01); G06F 12/00 (2006.01); G06F 12/16 (2006.01); G06F 13/16 (2006.01)
CPC G06F 12/0246 (2013.01) [G06F 3/061 (2013.01); G06F 3/0631 (2013.01); G06F 3/064 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 12/00 (2013.01); G06F 12/16 (2013.01); G06F 3/0608 (2013.01); G06F 3/0611 (2013.01); G06F 3/0638 (2013.01); G06F 3/0644 (2013.01); G06F 3/0665 (2013.01); G06F 3/0688 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/214 (2013.01); G06F 2212/7202 (2013.01); G06F 2212/7205 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A memory system comprising:
a nonvolatile semiconductor memory including a plurality of regions, the regions including one or more first regions, a plurality of second regions being different from the first regions, and a third region being different from the second regions; and
a controller being configured to:
receive a write request from a host device, the write request designating a size of first data;
perform a first operation of writing the first data to the first regions in response to the write request; and
perform a second operation of transferring second data stored in the second regions to the third region that stores no valid data and treating the second regions as free regions, wherein
the controller is configured to perform at least a part of the second operation during a period of time starting from the receiving of the write request and ending at a completion of the first operation of writing the first data.