US 12,259,812 B2
Center allocation data structure
Leon Zlotnik, Camino, CA (US); and Brian Toronyi, Boulder, CO (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 18, 2022, as Appl. No. 17/867,375.
Prior Publication US 2024/0020223 A1, Jan. 18, 2024
Int. Cl. G06F 12/02 (2006.01); G06F 9/50 (2006.01)
CPC G06F 12/023 (2013.01) [G06F 9/5016 (2013.01); G06F 12/0292 (2013.01)] 23 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory resource; and
a processing device coupled to the memory resource, wherein the processing device is configured to:
write a first data entry to an address location of the memory resource that is neither a first physical address of the memory resource nor a last physical address of the memory resource;
determine whether a second data entry to be written to the memory resource has a value that is greater than a value of the first data entry or a value that is less than the value of the first data entry; and
in response to a determination that the second data entry has the value that is greater than a value of the first data entry, write the second data entry to an address location of the memory resource that is physically located between the address location of the memory resource to which the first data entry is written and the last physical address of the memory resource; or
in response to a determination that the second data entry has the value that is less than the value of the first data entry, write the second data entry to an address location of the memory resource that is physically located between the address location of the memory resource to which the first data entry is written and the first physical address of the memory resource.