| CPC G06F 11/076 (2013.01) [G06F 11/073 (2013.01); G11C 29/025 (2013.01); G11C 29/08 (2013.01); G11C 29/44 (2013.01); G11C 29/52 (2013.01)] | 16 Claims |
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1. A method for operating a memory system, comprising:
performing, in a memory cell array in which a plurality of word lines and a plurality of bit lines intersect with each other, a word line verification by deactivating each of the plurality of word lines and at the same time performing a bit line equalization;
determining a fail bit count for each of the plurality of word lines according to a number of bit flips that occurred in memory cells corresponding with that word line during the word line verification; and
determining a degraded word line on the basis of fail bit counts of the plurality of word lines,
wherein determining the degraded word line comprises:
determining whether a second word line selected from among the plurality of word lines satisfies a first condition, the first condition being satisfied for a word line when a fail bit count of that word line is larger than a first threshold count;
determining whether the second word line satisfies a second condition, the second condition being satisfied for a word line when the fail bit count of that word line is larger than a sum of a second threshold count and a maximum fail bit count between fail bit counts of word lines adjacent to that word line; and
determining whether the second word line is the degraded word according to whether the second word line satisfies both the first and second condition.
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