US 12,259,777 B2
Uncorrectable memory error prediction
Shen Zhou, Shanghai (CN); Xiaoming Du, Shanghai (CN); Cong Li, Shanghai (CN); Kuljit S. Bains, Olympia, WA (US); Rajat Agarwal, Portland, OR (US); Murugasamy K. Nachimuthu, Beaverton, OR (US); Maciej Lawniczak, Gdansk (PL); Chao Yan Tang, Shanghai (CN); and Mariusz Oriol, Gdynia (PL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 15, 2021, as Appl. No. 17/348,435.
Prior Publication US 2023/0083193 A1, Mar. 16, 2023
Int. Cl. G06F 11/07 (2006.01); G11C 29/44 (2006.01); G11C 29/52 (2006.01)
CPC G06F 11/076 (2013.01) [G06F 11/073 (2013.01); G06F 11/0751 (2013.01); G11C 29/44 (2013.01); G11C 29/52 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus to predict memory device failure, comprising:
a substrate; and
a controller disposed on the substrate, the controller to execute a memory failure prediction engine, the memory failure prediction engine to correlate a hardware configuration of a memory device with correctable errors (CEs) detected by an on-die error checking and correction (ECC) circuit of the memory device and provided to the controller by the memory device, and predict an uncorrectable error (UE) based on correlation of the hardware configuration with the detected CEs.