US 12,259,775 B2
Power optimized timer module for processors
Anthony Giardina, Colfax, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 18, 2021, as Appl. No. 17/323,793.
Prior Publication US 2022/0374065 A1, Nov. 24, 2022
Int. Cl. G06F 1/329 (2019.01); G06F 1/3206 (2019.01); G06F 1/3234 (2019.01)
CPC G06F 1/329 (2013.01) [G06F 1/3206 (2013.01); G06F 1/3243 (2013.01); Y02D 10/00 (2018.01)] 16 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a processor circuitry to execute one or more instructions, wherein the processor circuitry is to configure a plurality of parameters for each timer event, and provide the plurality of parameters to an application programming interface; and
a timer circuitry to receive the plurality of parameters that are configured by the processor circuitry, and to batch a plurality of timer events according to the plurality of parameters, wherein the plurality of parameters comprises a long-term quantity requirement for each timer event of the plurality of timer events.